The need for greater radio frequency (RF) bandwidth for many applications is one of these chicken and egg things in technology. What came first? Was it the bandwidth - or the need for the bandwidth?
You could argue that this paradox has either driven, or been enabled by, modern devices such as the Texas Instruments ADC12DJ3200. This device is the analog-to-digital converter used on the recently-released Abaco FMC134 with sample rates up 6.4GSPS with 12-bits. That’s over 12 GBytes/second per channel with encoding and word alignment. The FMC134 can run at these rates with two channels using 16 JESD204B lanes, so the FPGA must consume and process over 24GBytes/second to fully take advantage of this capability.
Often, this is accomplished by pushing this data onto extremely wide internal data buses inside the FPGA. This is kind of like merging an Autobahn in Germany onto a 12-lane freeway in Houston, Texas; you’re going to need a lot of width.
Fortunately, FPGA innovators like Xilinx have a steady stream of bigger and bigger FPGAs with more and more resources - such as the Virtex Ultrascale class devices used on the Abaco VP880. Even with this huge FPGA, there’s only so much that can be done on a single payload module in a system. Often, once data is reduced, it is passed to a processor for more analysis.
The theoretical maximum transfer bandwidth of PCIe Gen 3 x8 is 8GBytes/second. However, in reality, there are inefficiencies and this rate is rarely achieved. So here’s our proverbial “connecting a fire hose into a garden hose”: with 24GBytes/second coming in, and often under 6GBytes/second going out, we must reduce data on the FPGA to a manageable level to keep up. If an application needs to move more data than PCIe can handle – what do we do?
The obvious answer is, of course, adding a faster interface. One such solution is using fiber optics like those defined under VITA 66.4. This is a new standard from VITA for VPX backplanes that enables support for up to 12 high speed serial lanes per block. We recently added this feature to the VP880 with the use of our ‘Blast’ technology.
If you look at the VP880 block diagram, we include a configurable site that makes it possible to add more features such as memory or a Firefly fiber optic interface routed to a VITA 66.4 connection. The underlying Firefly technology used gives us up to 14 Gigabits/second per lane. With 12 lanes on the VP880, we can now get up to 21 GBytes/second out of our FPGA. While this isn’t our full 24 GBytes/second fire hose from the FMC134, it’s no garden hose either.
It’s interesting to see these trends in processing technology. Faster data requires bigger FPGAs and large pipes to move the data, requiring more parallel processing on the CPU and GPU side. But, as I’ve said many times – most recently in a recent webinar with Open Systems Media: use the right tool for the job. At Abaco, we’re continuing to follow the trends and provide innovative solutions for our customers to meet their most demanding high performance embedded computing needs. The VP880, FMC134, and VITA 66.4 are just some examples of new solutions to those fire hose problems.